A set-associative cache memory has two critical timing paths; the cache array access path and the directory/TLB look up path (i.e. the hit logic path). For a read operation, in order to speed up the cache access, the hit logic operation and the cache array read operation are usually overlapped in time. That is, both operations are performed in parallel during the same clock cycle. Depending on the cache array size or the directory/TLB configuration, either one of them can be limiting the system cycle time. The selected set identification signals from the hit logic path usually come late, at the end of the cache access cycle. These select signals enable an output from one of the sets that make up the set associative cache, for example one of four sets or one of eight sets. The late select function and its circuit implementation are a very important part in the overall cache performance. In prior art designs, the late select implementation is generally complex in terms of circuit implementation and the use of clock signals for timing.